Freescale MPC8349E数字家庭方案

       Freescale 公司的MPC8349-mITX数字家庭參考设计平台采用MPC8349E PowerQUICC II™ Pro系列统信处理器。

        它采用片上系统（SoC）架构，集成了增强e300核和先进的特性如DDR存储器，双吉比特以太网，双PCI和高速USB控制器。时钟速率可高达667 MHz，是最高性能的PowerQUICC II器件。MPC8349E可广泛应用在以太网路由器和交换器，无线LAN (WLAN)设备，网络存储，家庭网络，工业控制以及复印机，打印机和其它图像设备。本文介绍了MPC8349E的主要性能和方框图以及MPC8349-mITX数字家庭參考设计平台的主要性能和方框图。

       The MPC8349E PowerQUICC II™ Pro family of integrated communications processors is a next-generation extension of the popular PowerQUICC II line. Based on a system-on-chip (SoC) architecture, the MPC8349E PowerQUICC II Pro Family integrates the enhanced e300 core and advanced features, such as DDR memory, Dual Gigabit Ethernet, Dual PCI and Hi-Speed USB controllers. With clock speeds scaling to 667 MHz, the MPC8349E family of processors offers the highest performing PowerQUICC II devices available.

       The MPC8349E PowerQUICC II Pro Family is designed to provide a cost-effective, highly integrated control processing solution that addresses the emerging needs of networking, communications and pervasive computing applications. MPC8349E processors can be used in applications such as Ethernet routers and switches, wireless LAN (WLAN) equipment, network storage, home network appliances, industrial control equipment, and copiers, printers and other imaging systems.

      e300 SoC Platform

       The MPC8349E PowerQUICC II Pro Family is based on the e300 SoC platform—making it easy and fast to add or remove functional blocks and develop additional SoC-based family members targeting emerging market requirements. At the heart of the e300 SoC platform is Freescale Semiconductors e300 core. Based on the classic instruction-set architecture, the e300 core is an enhanced version of the 603e core used in previous-generation PowerQUICC II processors. Enhancements include twice as much L1 cache (32 KB data cache and 32 KB instruction cache) with integrated parity checking, and other performance-enhancing features. The e300 core is completely software-compatible with existing 603e core-based products.

      Integrated Security

       The MPC8349E Family features a powerful integrated security engine derived from Freescale Semiconductors security coprocessor product line. The MPC8349E Familys security engine supports DES, 3DES, MD-5, SHA-1, AES, and ARC-4 encryption algorithms, as well as a public key accelerator and an on-chip random number generator. The security engine is capable of single-pass encryption and authentication, as required by IPsec, IEEE® 802.11i standard and other security protocols.

                                                    图1. MPC8349EA方框图

       MPC8349EA主要特性：

       Major features of the MPC8349EA are as follows:
       Embedded PowerPC e300 processor core; operates at up to 667 MHz
       High-performance, superscalar processor core
       Floating-point, integer, load/store, system register, and branch processing units
       32-Kbyte instruction cache, 32-Kbyte data cache
       Lockable portion of L1 cache
       Dynamic power management
       Software-compatible with the other Freescale processor families that implement Power Architecture technology
       Double data rate, DDR1/DDR2 SDRAM memory controller
       Programmable timing supporting DDR1 and DDR2 SDRAM
       32- or 64-bit data interface, up to 400 MHz data rate
       Up to four physical banks (chip selects), each bank up to 1 Gbyte independently addressable
      DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
      Full error checking and correction (ECC) support
      Support for up to 16 simultaneous open pages (up to 32 pages for DDR2)
       Contiguous or discontiguous memory mapping
      Read-modify-write support
      Sleep-mode support for SDRAM self refresh
       Auto refresh
       On-the-fly power management using CKE
       Registered DIMM support
        2.5-V SSTL2 compatible I/O for DDR1, 1.8-V SSTL2 compatible I/O for DDR2
      Dual three-speed (10/100/1000) Ethernet controllers (TSECs)
      Dual controllers designed to comply with IEEE 802.3®, 802.3u®,     820.3x®, 802.3z®,
      802.3ac® standards
      Ethernet physical interfaces:
      1000 Mbps IEEE Std. 802.3 GMII/RGMII, IEEE Std. 802.3z TBI/RTBI, full-duplex
      10/100 Mbps IEEE Std. 802.3 MII full- and half-duplex
       Buffer descriptors are backward-compatible with MPC8260 and MPC860T 10/100
       programming models
       9.6-Kbyte jumbo frame support
       RMON statistics support
       Internal 2-Kbyte transmit and 2-Kbyte receive FIFOs per TSEC module
       MII management interface for control and status
      Programmable CRC generation and checking
      Dual PCI interfaces
      Designed to comply with PCI Specification Revision 2.3
      Data bus width options:
      Dual 32-bit data PCI interfaces operating at up to 66 MHz
      Single 64-bit data PCI interface operating at up to 66 MHz
      PCI 3.3-V compatible
      PCI host bridge capabilities on both interfaces
      PCI agent mode on PCI1 interface
      PCI-to-memory and memory-to-PCI streaming
      Memory prefetching of PCI read accesses and support for delayed read transactions
      Posting of processor-to-PCI and PCI-to-memory writes
     On-chip arbitration supporting five masters on PCI1, three masters on PCI2
     Accesses to all PCI address spaces
     Parity supported
     Selectable hardware-enforced coherency
     Address translation units for address mapping between host and peripheral
     Dual address cycle for target
     Internal configuration registers accessible from PCI
     Security engine is optimized to handle all the algorithms associated with IPSec, SSL/TLS, SRTP, IEEE Std. 802.11i®, iSCSI, and IKE processing. The security engine contains four crypto-channels, a controller, and a set of crypto execution units (EUs):
     Public key execution unit (PKEU) :
     RSA and Diffie-Hellman algorithms
     Programmable field size up to 2048 bits
     Elliptic curve cryptography
     F2m and F(p) modes
     Programmable field size up to 511 bits
     Data encryption standard (DES) execution unit (DEU)
     DES and 3DES algorithms
     Two key (K1, K2) or three key (K1, K2, K3) for 3DES
     ECB and CBC modes for both DES and 3DES
     Advanced encryption standard unit (AESU)
     Implements the Rijndael symmetric-key cipher
     Key lengths of 128, 192, and 256 bits
     ECB, CBC, CCM, and counter (CTR) modes
     XOR parity generation accelerator for RAID applications
     ARC four execution unit (AFEU)
     Stream cipher compatible with the RC4 algorithm
     40- to 128-bit programmable key
     Message digest execution unit (MDEU)
     SHA with 160-, 224-, or 256-bit message digest
     MD5 with 128-bit message digest
     HMAC with either algorithm
     Random number generator (RNG)
     Four crypto-channels, each supporting multi-command descriptor chains
     Static and/or dynamic assignment of crypto-execution units through an integrated      controller
     Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
     Universal serial bus (USB) dual role controller
     USB on-the-go mode with both device and host functionality
     Complies with USB specification Rev. 2.0
     Can operate as a stand-alone USB device
     One upstream facing port
     Six programmable USB endpoints
     Can operate as a stand-alone USB host controller
     USB root hub with one downstream-facing port
     Enhanced host controller interface (EHCI) compatible
     High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
     External PHY with UTMI, serial and UTMI+ low-pin interface (ULPI)
     Universal serial bus (USB) multi-port host controller
     Can operate as a stand-alone USB host controller
     USB root hub with one or two downstream-facing ports
     Enhanced host controller interface (EHCI) compatible
     Complies with USB Specification Rev. 2.0
     High-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operations
     Direct connection to a high-speed device without an external hub
     External PHY with serial and low-pin count (ULPI) interfaces
     Local bus controller (LBC)
     Multiplexed 32-bit address and data operating at up to 133 MHz
     Eight chip selects for eight external slaves
     Up to eight-beat burst transfers
     32-, 16-, and 8-bit port sizes controlled by an on-chip memory controller
     Three protocol engines on a per chip select basis:
     General-purpose chip select machine (GPCM)
     Three user-programmable machines (UPMs)
     Dedicated single data rate SDRAM controller
      Parity support
      Default boot ROM chip select with configurable bus width (8-, 16-, or 32-bit)
      Programmable interrupt controller (PIC)
      Functional and programming compatibility with the MPC8260 interrupt controller
      Support for 8 external and 35 internal discrete interrupt sources
      Support for 1 external (optional) and 7 internal machine checkstop interrupt sources
      Programmable highest priority request
      Four groups of interrupts with programmable priority
      External and internal interrupts directed to host processor
      Redirects interrupts to external INTA pin in core disable mode.
      Unique vector number for each interrupt source
       Dual industry-standard I2C interfaces
      Two-wire interface
      Multiple master support
      Master or slave I2C mode support
      On-chip digital filtering rejects spikes on the bus
      System initialization data optionally loaded from I2C-1 EPROM by boot sequencer embedded hardware
      DMA controller
      Four independent virtual channels
      Concurrent execution across multiple channels with programmable bandwidth control
       Handshaking (external control) signals for all channels: DMA_DREQ[0:3],
       DMA_DACK[0:3], DMA_DDONE[0:3]
       All channels accessible to local core and remote PCI masters
       Misaligned transfer capability
       Data chaining and direct mode
       Interrupt on completed segment and chain
DUART
      Two 4-wire interfaces (RxD, TxD, RTS, CTS)
       Programming model compatible with the original 16450 UART and the PC16550D
       Serial peripheral interface (SPI) for master or slave
       General-purpose parallel I/O (GPIO)
       64 parallel I/O pins multiplexed on various chip interfaces
       System timers
       Periodic interrupt timer
       Real-time clock
       Software watchdog timer
       Eight general-purpose timers
       Designed to comply with IEEE Std. 1149.1™, JTAG boundary scan
       Integrated PCI bus and SDRAM clock generation

       MPC8349E mITX数字家庭中心參考平台主要特性：
      MPC8349E mITX Digital Home Center Reference Platform features:
      MPC8349-mITX reference platform helps you manage your digital devices remotely   from just about anywhere on the globe. These include:
      Internet gateway
      Router
      Wi-Fi access point
      Digital content/media server
      Home automation
       PC
      Home-bound content remote access and sharing
       Backup Server
      The MPC8349E-mITX integrates the enhanced e300 PowerPC core and advanced features such as DDR memory, dual PCI, Gigabit Ethernet and high-speed USB controllers. The platform supports dual 10/100/1000 Mbps Ethernet controllers, dual 32-bit/single 64-bit PCI controllers, integrated security engines, USB 2.0 host and devices controllers, 4-channel DMA, DUART, serial peripherals, general purpose I/O and system timers. The high level of integration in the MPC8349E helps lower system costs, improves performance and simplifies board design. The MPC8349E also integrates a hardware encryption block that supports different algorithms for high-performance data authentication as required for secure communications in the residential market. It supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms in hardware.
      In addition to the highly integrated MPC8349E processor, the reference platform leverages external components to support these additional features:

       5-port Gigabit Ethernet switch 
       Four high-speed USB ports 
       Four Serial ATA ports 
       PCI slot 
       MiniPCI slot 
       Compact FLASH memory slot

图2. MPC8349E-mITX參考设计外形图

                                      图3. MPC8349E-mITX參考设计方框图

       Axentras Location-Free Access and Control Software:
      The HipServ software platform is a comprehensive and unified environment that allows home users to easily use various content on different devices within the home or access the content from anywhere, anytime. Home users are increasingly creating more digital content and need a single environment to better manage, access, share and backup their critical home-created content. This innovative software platform also allows users to access and share their home content using mobile devices.

       Key Features:
       Content remote access, sharing and publishing (home based content)
       Unified operating environment and interface for central access to any content
       Auto back-up from PC/Mac to central storage or remote storage
        Media management and server (UpnP-AV)
       Home surveillance (Internet camera)
      Remote desktop access (PC/Mac)
       Easy management of photos, music and videos

本文来源：Freescale     作者：

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